A low risk, low cost, royalty free architecture worth considering for high-performance custom ASICs is ”RISC-V”.
RISC-V is a free and open standard instruction set architecture enabling a new era of processor innovation. Based on RISC design principles it originated in the University of California, Berkeley in 2010. In the past decade, RISC-V has matured into a sophisticated standard for 32-, 64- and 128-bit processors and has achieved mainstream industry adoption in quite a short time. For example Nvidia will be using RISC-V onboard their GPUs. Western Digital has committed to switch upwards of a billion CPUs a year across all their storage products to RISC-V and has made their custom core hardware and associated software available to grow the ecosystem.
RISC-V enables reduced risk across a number of design considerations:
- The ecosystem is large, active and vibrant, and growing rapidly;
- The core ISA and extensions are standardized, and IP and toolchains are available from a number of vendors;
- The ISA design supports tailored and customising processors and instruction sets for their workload allowing rapid exploration of architectural/partitioning trade-offs;
- Security and privilege levels are a first-class design consideration – security is designed in from the onset.
A wide variety of standard operating systems, toolchains and debug tools are readily available on RISC-V, so developers will feel right at home.
When your design needs extra capabilities and greater compute envelope than a 16-bit MCU, why not consider RISC-V? Talk to Silansys about how we can develop a low-cost low-risk custom ASIC solution for your application. Silansys currently has ASIC’s in development from 0.18um to 12nm in a variety of applications with embedded CPU sub-systems, FPGA IP, DSP, hi-speed IO and mixed-signal sensors and power management.
Our longterm embedded firmware partner Emdalo Technologies is a member of the RISC-V International Association and has broad and extensive application expertise. Emdalo is an authorized design and training partner of Microchip and a member of the Mi-V Ecosystem and Mi-V Embedded Experts Network. Emdalo successfully customised Microchip’s PolarFire® SoC FPGA Linux® and its associated boot flow for Skycorp Inc.’s recent space-mission on the International Space Station (ISS) . Emdalo also provide training courses on RISC-V and have developed boot loaders, device drivers for RISC-V, and has contributed code upstream to the Linux kernel and qemu projects.
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